Integrated semiconducting components, known as chips, are employed in practically every modern electronic device. Each chip comprises a large number of individual components that have been fabricated together on a small piece of semiconducting material to form a single circuit. The use of chips has made it possible to manufacture modern electronic devices that outperform, and are significantly more compact than, their predecessors.
A typical chip has a number of contact pads which are locations on the surface of the chip at which voltages are supplied and/or drawn from. Conductive leads provide electrical paths between each contact pad and conductors on a printed wiring board on which the chip is mounted. Frequently, two leads are required for each contact point-to-wiring board conductor connection. A first lead, an inner lead, typically a very thin wire, is bonded to the chip contact pad. The inner lead is then bonded to a second lead, an outer lead, which is a reinforced metal lead or pin that, in turn, can be suitably bonded or attached to a terminal connected to the wiring board conductor. Leads are usually bonded to a chip as part of the post-fabrication packaging process wherein the chip is housed in a protective carrier. After packaging, the chip and inner leads are contained entirely in the carrier, and portions of the outer leads extend outward therefrom for bonding to the wiring board conductor terminals. Since two leads are required for each chip contact pad-to-wiring board conductor terminal connection, three separate bonds are required for each connection, namely, the chip contact pad to inner lead bond; the inner lead to outer lead bond; and the outer lead to conductor terminal bond.
Performing the bonding needed for chip-to-wiring board connections is a delicate process. This is in part because each bond, especially the contact pad to inner lead bond, is between two very small pieces, and must be performed without affecting other bonds located in very close proximity thereto. Moreover, housing the chip in the carrier may cause one or more of the leads bonded thereto to break or otherwise become disconnected. Also, there are additional elements of error in the inner lead-to-outer lead and outer lead-to-wiring board conductor terminal bonding processes. Thus, there is always the possibility that either during the chip lead bonding process, or during the processes of mounting the packaged component to wiring board mounting, one or more of the chip leads will be improperly bonded and a necessary chip-to-wiring board conductor connection won't be made.
Recent advances in electronic component manufacturing and assembly techniques have led to the development of automated equipment that performs the necessary lead bonding with a high degree of accuracy. However, automated equipment is not fail safe, and instances of faulty lead bonding still occur.
Therefore, an important part of the electronic device assembly processes is continuity testing. Continuity testing is performed to verify that the necessary lead bonding has been properly performed for each chip contact pad, and that a continuous electrical path exists between each chip contact pad and the wiring board conductor terminal it should be connected to. Continuity testing may also be performed after chip packaging to verify that the contact pad-to-lead bonds were properly formed. Continuity testing after chip mounting is one of the final inspections of an assembled electronic circuit performed in order to verify that the chips forming the circuit will operate properly.
Currently, continuity testing is performed by supplying a chip with test voltages and monitoring the result. This allows personnel operating the test equipment to verify the leads over which the test signals are supplied to the chip are properly bonded, and that leads over which the response signals from the chip are properly bonded. There are two ways to perform this type of continuity testing, namely, open testing and test pattern testing.
Open testing involves applying a test voltage to a single printed wiring board conductor connected to a chip and monitoring a second board conductor to detect an output signal. If no signal is detected, then one of the bonds, either the leads over which voltage is supplied to the chip or the leads over which voltage is propagated therefrom, is improperly bonded.
Unfortunately, open testing is not suitable for continuity testing chips which comprise most modern electronic devices. This is because there is usually more than one conductive path between the board conductor at which the test voltage is applied, and the board conductor at which the output signal is sensed. Thus, the output signal may be correctly detected even if one or more of the leads in the circuit is improperly bonded.
Continuity testing by applying a test pattern is an advanced form of open testing. In test pattern testing, a set of voltages comprising a test pattern is applied to the chip over a number of different board conductors connected thereto. A set of sensors connected to the board conductors extending from the chip monitor voltages comprising a response pattern which is produced by the chip in response to the test pattern.
There are limitations associated with test pattern continuity testing. Supplying test patterns is a time consuming process because a number of different test patterns may have to be supplied in order to generate at least one signal over each output lead. Moreover, the design of some chips may make it impossible to generate test patterns so that each signal is supplied to or read from each lead bonded to a chip. Also specific knowledge of the chip being tested must be known in order to perform test pattern testing which verifies that the response pattern is correctly generated.
Additional disadvantages are associated with test pattern continuity testing of Large Scale Integration (LSI) and Very Large Scale Integration (VLSI) chips. LSI chips and VLSI chips are the product of recent advances in semiconductor chip manufacturing. Each LSI and VLSI chip comprises thousands of individual components that have been fabricated together on a single section of semiconducting material. LSI and VLSI chips are able to perform more functions, and perform functions faster than earlier chips. The development of LSI and VLSI chips, and in the future Gigascale Integration (GSI) chips which comprise millions of components each, has and will continue to make further advances in electronics possible.
Test pattern continuity testing of LSI, VLSI and GSI chips is unsuitable for a number of reasons. Each of these chips may be connected to a hundred or more leads that are required for all the input and output electrical connections the chip needs to operate. Consequently, performing a continuity test by supplying test patterns would take a significant amount of time in order to apply all the test patterns to the input leads in order to get the desired results from all the output leads. Moreover, providing and operating equipment that can generate the necessary test patterns can be costly. Also, many of these chips include what are referred to as "dynamic" components, that require producing a large number of test patterns during a short period of time in order to generate a large number of response patterns, also produced during a short period of time. Providing and operating testing devices that can rapidly generate the required test patterns, and that monitor the rapidly changing response patterns, is costly.